1. Field of the Invention
The present invention relates to a method of generating a standard cell layout, and more particularly, to a method that pieces together a plurality of leaf cell layouts to form a standard cell layout.
2. Description of the Prior Art
Standard cells e.g. logic cells are indispensable in integrated circuits. Currently, the layout of each particular standard cell is created manually. However, there are hundreds of different types of standard cells, and therefore it is time-consuming to create a standard cell layout library in which the layouts of all different types of standard cells are collected.
With the emergence of new functionality and the advance of semiconductor fabrication technology, new standard cells are designed unceasingly and the original standard cell layouts have to be modified. According to the conventional layout generation method, every new standard cell layout or an original standard cell layout having a minor modification has to be created manually, which is a time-consuming task.